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1-29 avs technology inc. 4110 clipper ct., fremont ca94538 tel: (510) 353-0848 fax: (510) 353-0856 january 22, 2004 features ? complete dac and adc audio codec with headphone driver. ? up to 96khz input sampling frequencies for adc/dac ? selectable dac de-emphasis filter. ? selectable adc high pass filter ? programmable audio data interface ? i 2 s, normal, left justified or dsp data for adc/dac ? 16,18, 20 and 24-bit input data resolution ? system clock: 64fs, 96fs,1 28fs, 192fs, 256fs or 384fs ? 250fs and 272fs system clock for usb application ? master or slave clocking mode ? regular audio or usb mode audio ? 2 or 3-wire software control interface selectable by external pin. ? 2 channel microphone or line inputs ? programmable power down features to conserve power general ? 2.7-volt to 3.6-volt power supply range (tbd) ? 28-pin ssop package applications ? low cost, cd-quality consumer audio equipment ? portable mp3 players and recorders advance product information. avs reserves the right to modify this product without notice. description the AV2722 is a mixed signal cmos monolithic device which is a low cost audio codec designed with a built-in headphone driver. it supports regular audio or usb mode audio and is therefore ideal for portable mp3 audio and speech players and recorders. it can also be used for mini- disk, cd-rw machines. stereo line audio inputs with programmable gain are provided a microphone bias voltage output is also provided which makes the AV2722 ideal for an electret type microphone. for the multi-bit signal delta dac, 64x oversampling digital interpolation filter is used with programmable de-emphasis, volume control, and sampling rate selection features. the dac supports i2s, normal, left justified or dsp data with 16, 18, 20 and 24-bit resolution. sampling rates from 8khz to 192 khz are supported. at the dac output, stereo headphone drivers are built in for driving headphones. for the multi-bit delta-sigma adc, programmable gain are provided at the input. state of the art decimation filter is used to down-sample the received signal and finally a selectable high pass filter is used to reduce un-wanted low frequency noise. the digital audio serial output can be programmed at various formats similar to the dac input. avs technology audio codec with headphone driver and programmable sample rates AV2722 d r aft audio serial port multi-level delta-sigma modulator dac sdi sfda sfad xck vdd vddh aoutl AV2722 block diagram audio serial port decimation digital filter multi-level delta-sigma modulator adc input output high pass filter houtl dac aoutr houtr ainl ainr adc vcm micbias hpvr hpdet d i g i t a l a u d i o i / o i n t e r f a c e sc sdo 2 or 3 wire serial command port sda scl csb mode vdda vss vssh vssa vssa rs/ clock generator interpolation digital filter low pass filter low pass filter headphone driver headphone driver volume control gain control gain control
AV2722 (preliminary) 2-29 january 22, 2004 pin configuration ordering information product package temperature range AV2722 28-pin ssop -25 to +85 o c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 18 16 15 21 23 22 20 19 17 24 25 28 27 26 vdd sc sdi sfda sdo sfad hpvr vddh houtl houtr vssh aoutl aoutr vdda rs/ sda mode hpdet ainl micbias vssa vssa vcm ainr csb scl xck vss AV2722
AV2722 (preliminary) 3-29 january 22, 2004 pin assignments pin no. pin name type description 1 vdd supply power supply for digital circuits 2 sc digital input/output dac serial input data bit clock. it is input for slave mode and output for master mode. 3 sdi digital input dac serial input data. it can be in normal, left ju stified, i2s, or dsp type 4 sfda digital input/output dac samp le rate clock. it is input for slave mode and output for mas- ter mode. for normal or left-justified type sdi data input, a high in sfda indicates left channel data, a low in sfda indicates right chan- nel data. for i2s type, a low in sfda indicates left channel data, a high in sfda indicates right channel data.for dsp mode, a?sync? pulse in sfda is followed by two da ta words, left channel data is fol- lowed by right channel data. 5 sdo digital output adc serial output data. it ca n be in normal, left ju stified, i2s, or dsp type. 6 sfad digital input/output adc sample rate clock. it is input for slave mode and output for mas- ter mode. for normal or left-justified type sdo data output, a high in sfad indicates left channel data, a low in sfad indicates right chan- nel data. for i2s type, a low in sfad indicates left channel data, a high in sfad indicates right channel data. for dsp mode, a?sync? pulse in sfad is followed by two dat a words, left channel data is fol- lowed by right channel data. 7 hpvr analog output voltage referenc e for capless headpho ne connection.. 8 vddh supply power supply for headphone circuits. 9 houtl analog output left channel headphone output. 10 houtr analog output right channel headphone output. 11 vssh ground ground for headphone circuits. 12 aoutl analog output left channel audio line output. 13 aoutr analog output right channel audio line output. 14 vdda supply power supply for analog circuits. 15 vssa ground ground for analog circuits. 16 vssa ground ground for analog circuits 17 vcm analog output analog circuits common mode reference. 18 micbias analog output microphone bias. 19 ainr analog input right channel line/microphone input.
AV2722 (preliminary) 4-29 january 22, 2004 electrostatic discharge sensitivity this integrated circuits is manufactured on a cmos process. it can be da maged by esd. avs recommends that all integrated circuits be handled with appropriate esd precautions. improper hand ling and installation procedur es can cause damage to the device. 20 ainl analog input left channel line/microphone input 21 hpdet digital input headphone is plugged in or not plugged in indicator. the polarity of this signal can be inverted or not inverted, which is controlled by pro- gramming bit hpdetmode (creg4[2], address 04 hex), a logic ?low? inverts the polarity of hpdet into the chip. 22 mode digital input i2c or mpu control interf ace selection. if mode is logic ?high?, the chip is using mpu for chip programmi ng. if mode is logic ?low?, the chip is using i2c for chip programming. mode can be no-connect for mpu control due to the internal ?pullup? resistor. 23 csb digital input 3-wire mpu chip select, active low. 24 sda digital input/output 3-wire mpu data input /output or 2-wire i2c data input/output 25 scl digital input 3-wire mpu clo ck input /2-wire i2c clock input 26 rs/ digital input active low chip reset 27 xck digital input chip clock input. the clock rate of xck depends on the audio sam- pling rate, regular audio or usb audio. 28 vss ground ground for digital circuits pin no. pin name type description
AV2722 (preliminary) 5-29 january 22, 2004 xck systen clock requirement the system clock (xck at pin 27) for the AV2722 supports audio sampling rates from 64fs to 384fs for regular type audio, where fs is the audio sampling frequency (sfda /sfad), typically 8khz, 44.1khz, 48khz, 96khz, or 192khz. for usb type audio, sfda /sfad is either 250fs or 272fs. xck is used to operate the digital interpolation filter and the delta-sigma modulator. by using the two-wire (i2s) or 3-wire (mpu type) serial command port, user can program the chip to accept different clock frequency under different sampling rate. sampling rate xck clock freq uency (mhz) for regular mode adc dac 64fs 96fs 128fs 192fs 256fs 384fs 48khz 48khz n/a n/a n/a n/a 12.288 18.432 48khz 8khz n/a n/a n/a n/a 12.288 18.432 8khz 48khz n/a n/a n/a n/a 12.288 18.432 8khz 8khz n/a n/a n/a n/a 12.288 18.432 44.1khz 44.1khz n/a n/a n/a n/a 11.289 16.934 44.1khz 8khz n/a n/a n/a n/a 11.289 16.934 8khz 44.1khz n/a n/a n/a n/a 11.289 16.934 8khz 8khz n/a n/a n/a n/a 11.289 16.934 88.2khz 88.2khz n/a n/a 11.289 16.934 n/a n/a 96khz 96khz n/a n/a 12.288 18.432 n/a n/a off 192khz 12.288 18.432 24.57 6 36.864 49.152 73.728 sampling rate xck clock fr equency (mhz) for usb mode adc dac 250fs 272fs 48khz 48khz 12 n/a 48khz 8khz 12 n/a 8khz 48khz 12 n/a 8khz 8khz 12 n/a 96khz 96khz 12 n/a 44.1khz 44.1khz n/a 12 44.1khz 8khz n/a 12 44.1khz 8khz n/a 12 8khz 44.1khz n/a 12 8khz 8khz n/a 12 88.2khz 88.2khz n/a 12
AV2722 (preliminary) 6-29 january 22, 2004 sc sfda sfad sdi sdo AV2722 audio dsp processor AV2722 in master mode sdi audio data setup time sdi audio data hold time tm su tm hd sfda (pin 4) or sfad (pin 6) sc (pin 2) sdi (pin 3) sfda/sfad propagation delay from sc tm su tm hd tmsfd 10 ns 10 ns 10 ns audio data input timing - master mode tmsdod sdo propagation delay from sc (min) (min) (max) 10 ns sdo (pin 5) tmsdod tmsfd (max) master and slave mode operation - digital audio interface the AV2722 can be operated in either ma ster or slave mode. by default, the chip is set to operate in ?slave? mode. to configure the chip for ?master? mode operation, the programming bit master (creg6[7]) must be pro- grammed to ?1?. in master mode operation, AV2722 acts as a master which generates sc, sfad, and sfda. in slave mode operation, AV2722 receives these signa ls from an audio dsp encoder/decoder source.
AV2722 (preliminary) 7-29 january 22, 2004 sc sfda sfad sdi sdo AV2722 audio dsp processor AV2722 in slave mode sc pulse cycle time sc pulse width, high sc pulse width, low sdi audio data setup time sdi audio data hold time tsc tsch tscl tscsf tsfsc t su t hd sfda (pin 4) or sfad (pin 6) sc (pin 2) sdi (pin 3) sc to sfda / sfad edge sfda / sfad edge to sc tsc tsch tscl t su t hd tscsf tsfsc 50 ns (min) 20 ns 20 ns 10 ns 10 ns 10 ns 10 ns audio data input timing - slave mode tsdod sdo propagation delay from sc (min) (min) (min) (min) (min) (min) (max) 10 ns sdo (pin 5)
AV2722 (preliminary) 8-29 january 22, 2004 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 1/fs left channel right channel lsb msb msb lsb lsb lsb msb msb 22 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 lsb msb msb lsb lsb lsb msb msb 22 2 1 0 2 1 0 2 1 0 2 1 0 sfda (pin4) or sfad (pin 6) sc (pin 2) sdi (pin3) (16-bit audio data) (18-bit audio data) (20-bit audio data) (24-bit audio data) "normal" data input timing sdi (pin3) sdi (pin3) sdi (pin3) 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 1/fs left channel right channel lsb msb msb lsb lsb lsb msb msb 22 sfda (pin 4) or sfad (pin 6) sc (pin 2) sdi (pin 3) (16-bit audio data) (18-bit audio data) (20-bit audio data) (24-bit audio data) 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 lsb msb msb lsb lsb lsb msb msb 22 "i s" data input timing 2 sdi (pin 3) sdi (pin 3) sdi (pin 3) i2s mode in i2s mode, the msb of the audio data sdi is sampled on the second rising edge of sc following sfda/sfad transition. sfda/sfad are low during the left channel samples and high during the right channel samples. normal mode in normal mode, the audio data, sdi, is right-justified. the lsb are aligned with the rising/falling edge of sfda/ sfad. data is latched into the chip on the rising edge of sc. sfda/sfad are high during the left channel samples and low during the right channel samples.
AV2722 (preliminary) 9-29 january 22, 2004 left justified mode in left justified mode, the msb of t he audio data sdi is sampled on the first rising edge of sc following sfda/ sfad transition. sfda/sfad are high during the left channel samples and low during the right channel samples. dsp mode in dsp mode, the audio data sd is in time division mult iplexed format. the left and right channel data are shifted into the chip in sequence with the left channel data first followed by the right channel data. sfda/sfad is a ?sync? pulse which appears every 1/fs time. the mini mum sfda/sfad sync-pulse is one sc cycle. 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 1/fs left channel right channel lsb msb msb lsb lsb lsb msb msb 22 sfda (pin 4) or sfad (pin 6) sc (pin 2) sdi (pin 3) (16-bit audio data) (18-bit audio data) (20-bit audio data) (24-bit audio data) 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 lsb msb msb lsb lsb lsb msb msb 22 "left justified" data input timing sdi (pin 3) sdi (pin 3) sdi (pin 3) 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 1/fs lsb msb msb lsb lsb lsb msb msb 22 15 14 0 1 2 0 1 2 17 0 1 2 19 16 0 1 2 21 18 23 lsb msb msb lsb lsb lsb msb msb 22 sfda (pin 4) or sfad (pin6) sc (pin 2) sdi (pin3) dsp mode timing left channel right channel left channel left channel right channel right channel right channel left channel (16-bit audio data) (18-bit audio data) (20-bit audio data) (24-bit audio data) 15 17 19 23 no valid data no valid data no valid data no valid data 1 sc sdi (pin3) sdi (pin3) sdi (pin3)
AV2722 (preliminary) 10-29 january 22, 2004 1 0 0 0 r/w 3-wire mpu- type serial control port timing diagram sda scl d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 csb chip id 5-bit address 8-bit data chip id chip id, d[15:14] =10 read /write d[13] = 0 for write address, [12:8] = 00010 data, d[7:0] = 0000_0100 0 0 1 0 0 00 0 0 1 0 0 software control interface the AV2722 programmable registers can be programmed via the software control interface. either 3-wire (mpu type) or 2-wire (i2s) interface are supp orted. the mode pin sets the select ion of the software control interface. 3-wire serial command port by default, the AV2722 is set to use the 3-wire, micropro cessor-type interface (mpu). because mode pin is inter- nally pulled up to default the chip in mpu programming mo de. therefore, the mode pi n can be ?no-connect? if mpu interface is used. the 3-wire serial command port rece ives serial input data (sda), serial input clock (scl) and active low chip select (csb). the serial data is clocked in by the rising edge of the serial input clock if csb is low. the 16 bit serial input data contains 8 address control bits followed by 8 data bits. the address control bits are: d[15:14] - chip id. (for the AV2722, chip id is binary ?10?) d[13] - read/write control bit. (for the AV2722, d[13]=1 for read and 0 for write) d[12:8] - 5-bit programmable register address. the data bits are:d[7:0] - 8 bit data. an example is given to write into address ?00010? with data ?0000_0100?. mode (pin no. 22) software control interface 0 2-wire i2s 1 3-wire mpu type
AV2722 (preliminary) 11-29 january 22, 2004 csb (pin23) scl (pin 25) sda (pin24) 3-wire mpu-type serial control port timing requirement tsclcsb t csbl t csbh t sclh scll t t sdasu t sdahd t scl tcsbscl
AV2722 (preliminary) 12-29 january 22, 2004 2-wire (i2c) serial command port the AV2722 also provides a 2-wire i2c serial command port for chip programming. user can use this port to program the internal control registers. the chip address for the AV2722 is a 7-bit hexadecimal number ?32hex?. the protocol for write operation consis ts of sending 3 bytes of data to t he AV2722 at the sda pin. following each byte is the acknowledge generated by the AV2722. the firs t byte is the 7-bit chip address followed by the read/ write bit (read is logic ?high? and write is logic ?low?) t he second byte is the AV2722 control register address. the third byte is the control regi ster data. an example which illustrates ?write ? timing of register address 00h and data 30h is given below. to use the 2-wire i2c serial command port, the mode pi n must be connected to ground through a pulldown resis- tor. upon power up, all programming registers are set to default values. by default, or without using i2c or mpu-type port, the AV2722 is set ready to run 256fs clock frequency with 44.1k or 48k sampling rate, and to accept 24-bit, ieft justitied data, with de-e mphasis filtering turns off. 1 1 00 1 0 0 ca0 r/w ack a7 a6 a5 a4 a3 a2 a1 a0 ack d1 d2 d3 d4 d5 d6 d7 d0 ca6 start ack stop chip address: ca[6:0]=011_0010 register address: a[7:0]= 00h data: d[7:0] = 30h i2s - serial command port timing diagram sda scl t buf t high t low t hd;dat t su;dat t r t f t hd;sta t su,sta t hd; sta t su,sto t r p p s sr sda scl i2s - serial command port timing requirement
AV2722 (preliminary) 13-29 january 22, 2004 regular or usb audio data the AV2722 can be operated in regular (non-usb) or usb (universal serial bus) modes. the usage of regular or usb applications are programmed via the 3-wire or 2-wire serial command port. the selection of sampling rates for regular or usb modes are controlled by creg3[7:0]. pleas e refer to the section ?programmable control register assignment? below. in regular audio application, the user selects an a ppropriate xck clock which is gene rated by an off chip oscilla- tor.the user then program the chip for desired adc, dac sa mpling frequencies. by default, the chip is set to oper- ated at 48khz sampling rate, 256fs for both the adc and dac, with xck running at 12.288 mhz. the AV2722 supports sampling rates from 8khz to 96 khz for both adc and dac. for 192 khz sampling rate, only the dac path is operational. the adc path is ?turned off?. in usb system, the common usb clock frequency is 12 mhz. to use the AV2722 for usb application, xck should be running at 12 mhz. programmable control register assignment the are 13 programmable registers in the AV2722. the fu nction and address assignme nt of these registers are described in the following table. all these programmable registers can be read back via the serial command port. address (7-bit hex) register default value (hex) register function 0 volreg[7:0] 7f volume value for both left and right channel 1 creg1[7:0] 00 de-emphasis control 2 creg2[7:0] 00 dac path se rial input port control 3 creg3[7:0] 00 dac, adc sampling frequency selection control 4 creg4[7:0] 00 dac and miscellaneous power down control 5 creg5[7:0] 40 dac headphone control 6 creg6[7:0] 00 adc path seri al output port control 7 creg7[7:0] 03 adc high-pass filter control 8 creg8[7:0] 12 adc path left c hannel gain and mute control 9 creg9[7:0] 12 adc path right channel gain and mute control a creg10[7:0] 06 adc power down control b creg11[7:0] 00 adc path left and right microphone gain control c creg12[7:0] 00 chip software reset
AV2722 (preliminary) 14-29 january 22, 2004 address 00, volume regi ster (creg0[7:0]) volume[7:0]: control the volume of the left and righ t dac channels concurrently. default value is 8?h7f. address 01, de-emphasis cont rol register (creg1[7:0]) deemp:de-emphasis control 0: by-pass the de-emphasis filter in the dac path (default). 1: enable the de-emphasis filter in the dac path. address 02, dac path seria l input port co ntrol register (creg2[7:0]) bpf48: bit per sfda/sfad frame control 0: bit per frame is 64 bit, i.e. 32-bit for the left channel an d 32-bit for the right channel for the sd input and sdo output. 1:bit per frame is 48 bit, i.e. 24-bit for the left channel and 24-bit for the right channel for the sd input and sdo output. dahrsc: dacs use higher rate sc 0: dac path uses whatever sc is provi ded, either master or slave mode (default). 1: dac path uses higher rate sc. when the adc path is at higher sampling than the dac path, program this bit to ?1? allows sd input to come in at the higher sc rate. dasfdly: delay sfda by 1 sc in the dac path. 0: do not delay the sfda by 1 sc cycle (default). 1: delay the sfda by 1 sc cycle. dainvsc: invert the sc bit clock. 0: do not invert the sc bit clock (default). 1: invert the sc bit clock. a[7:0] creg0[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 00 volume[7:0] default value 01111111 a[7:0] creg1[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 01 reserved deemp default value 00000000 a[7:0] creg2[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 02 bpf48 dahrsc das fdly dainvsc damode[1:0] daformat[1:0] default value 00000000
AV2722 (preliminary) 15-29 january 22, 2004 damode[1:0]: these two bits define the dac path serial data input mode. 00: left justified mode (default). 01: i2s mode. 10: normal mode 11: dsp mode daformat[1:0]: these two bits define the audio serial input data bit length. 00: 24 bits (default). 01: 20-bits. 10: 18 bits. 11: 16 bits. address 03, dac, adc sampli ng frequency selection co ntrol register (creg3[7:0]) the freqcon[5:0] are used to set up the device to work under different xck clock rate and various sampling rate combinations. the following table defines programming values under different xck and sampling rate conditions.there are 26 various cases for regular (non-usb) mode and 10 various cases for usb mode. a[7:0] creg3[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 03 reserved freqcon[5:0] default value 0000 0 000
AV2722 (preliminary) 16-29 january 22, 2004 regular (non-usb) mode frequency control register settings sampling rate xck frequency sfda sfad frequency control register programming values adc dac freqcon[5:0] khz khz mhz no. of xck no. bit5 bit4 bit3 bit2 bit1 bit0 48 48 12.288 256 0000000 48 48 18.432 384 1000001 48 8 12.288 256 2000010 48 8 18.432 384 3000011 8 48 12.288 256 4000100 8 48 18.432 384 5000101 8 8 12.288 256 6000110 8 8 18.432 384 7000111 44.144.1 11.289 256 8001000 44.144.1 16.934 384 9001001 44.1 8 11.289 256 10001010 44.1 8 16.934 384 11001011 8 44.1 11.289 256 12001100 8 44.1 16.934 384 13001101 8 8 11.289 256 14001110 8 8 16.934 384 15001111 88.288.2 11.289 128 16010000 88.288.2 16.934 192 17010001 96 96 12.288 128 18010010 96 96 18.432 192 19010011 off 192 12.288 64 20010100 off 192 18.432 96 21010101 off 192 24.576 128 22010110 off 192 36.864 192 23010111 off 192 49.152 256 24011000 off 192 73.728 384 25011001
AV2722 (preliminary) 17-29 january 22, 2004 address 04, dac and miscellaneous power down control register (creg4[7:0]) pwdnpullupr: power down pullup resistor at the mode pin. 0: turn on the pullup resistor at the mode pin (default). 1:disable the pullup resi stor at the mode pin. this bit is used to reduce power consumption in the pullup resi stor at the mode pin if user uses i2c for chip programming. for i2c, the chip needs an external pulldown resistor at the mode pin. user can program this bit to ?1? to disable the internal pullup resistor. for user using t he 3-wire mpu interface, t he external pullup resistor is not needed. by default, the chip is i n mpu mode with the internal pullup resistor enabled. pwdncapless: power do wn the analog ?capless? circuit block. 0: do not power down the analog ?capless? circuit block (default). 1: power down the ?analog ?capless? circuit block. usb mode frequency control register settings sampling rate xck frequency sfda sfad frequency control register programming values adc dac freqcon[5:0] khz khz mhz no. of xck no. bit5 bit4 bit3 bit2 bit1 bit0 48 48 12 250321 00000 48 8 12 250331 00001 8 48 12 250341 00010 8 8 12 250351 00011 96 96 12 250361 00100 44.144.1 12 272371 00101 44.1 8 12 272381 00110 8 44.1 12 272391 00111 8 8 12 272401 01000 88.288.2 12 272411 01001 a[7:0] creg4[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 04 reserved pwdnpullupr pwdncapless pwdnvcm pwdnline hpdetmode capless mute default value 00 000000
AV2722 (preliminary) 18-29 january 22, 2004 this bit must be used together with ?capless? (creg4[1]) for he adphone output application. if user is using external coupling capacitors at headphone output pins hpoutl and hpoutr, capless should be programmed to ?1? (capless circuit block is not used), pwdncapless should be programmed to ?1? to conserve power consumption. pwdnvcm:power down the resistor at th e analog common mode voltage reference. 0: do not power down the resistor at the analog common mode voltage reference(default). 1: power down the resistor at the analog common mode voltage reference. pwdnline:power down the line outputs simultaneously. 0: do not power down the line outputs (default). 1: power down the line outputs simultaneously. when headphone is used, this bit must be progra mmed to ?1? to conserve power consumption. hpdetmode:headphone detection mode. 0: invert the hpdet pin sign al inside the chip (default). 1: do not invert the hpdet pin signal inside the chip. this bit provides the flexibility to invert or not invert the hpdet pin signal inside the chip. capless: external coupling capaci tor of headphone is us ed or not used at hpoutl and hpoutr. 0: external coupling capacitor is not used, the chip internal ?capless? circuit block is needed (default). 1: external coupling capacitor is used, the chip internal ?capless? circuit block is not needed. this bit must be programmed together with pwdncapless (cre g4[5]). by default, external coupling capacitor at headphone outputs are not used. if they are used, both capless a nd pwdncapless must be programme d to ?1? to conserve power consumption mute: mute the dac aoutl and aoutr outputs 0: do not mute the dac aoutl and aoutr outputs (default). 1: mute the dac aoutl and aoutr outputs, t he headphone hpoutl and hpoutr are not ?muted?. . address 05, dac path headphone control register (creg5[7:0]) hpagcd[6:0]: 7-bit headphone automatic gain control ag c data. default value of hp agcd[6:0] is hex40 which is 0 db. a[7:0] creg5[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 05 reserved hpagcd[6:0] default value 01 000000
AV2722 (preliminary) 19-29 january 22, 2004 address 06, adc path seria l output port control register (creg6[7:0]) master: master or slave mode control 0: the chip is operated as ?slave?. in slave mode, AV2722 accepts sfda, sfad, and sc. 1:the chip is operated as ?master?. in mast er mode, AV2722 generates sfda, sfad and sc. in either mode, dac and adc can be operated at different sampling rate. adhrsc:adcs use higher rate sc 0:adc path uses whatever sc is provided, either master or slave mode (default). 1:adc path uses higher rate sc. when the dac path is at higher sampling than the adc pat h, program this bit to ?1? allows sdo output to shift out data at the higher sc rate. adsfdly: delay sfad by 1 sc in the adc path. 0: do not delay the sf by 1 sc cycle (default). 1: delay the sfad by 1 sc cycle. adinvsc: invert the sc bit clock. 0: do not invert the sc bit clock (default). 1: invert the sc bit clock. admode[1:0]: these two bits define the adc path serial output data mode. 00: left justified mode(defalut). 01: i2s mode. 10: normal mode 11: dsp mode adformat[1:0]: these two bits define th e audio serial output data bit length. 00: 24 bits (default). 01: 20-bits. 10: 18 bits. 11: 16 bits. a[7:0] creg6[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 06 master adhrsc ads fdly adinvsc admode[1:0] adformat[1:0] default value 0 0 0 0 0000
AV2722 (preliminary) 20-29 january 22, 2004 address 07, adc path high pass filt er control register (creg7[7:0]) hpfosen: high-pass filter (hpf) offset enable in the adc path. 0: allow hpf to use previous stored data. 1: allow hpf to use new coming data. (default) hpfen: high-pass filter (hpf) enable in the adc path. 0: bypass the high-pass filter. 1: enable the high-pass filter (default). address 08, adc path left channel gain and mute control register (creg8[7:0]) adcmutel: adc left channel mute control. 0: do not mute the adc left channel (default). 1: mute the adc left channel, sdo will shift out all zero data in the left channel. adcgainl[4:0]: 5-bit adc left channel input gain (volume) control. the default value of adcgainl[4:0] is binary 10010 which is corresponding to 0 db. a[7:0] creg7[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 07 reserved hpfosen hpfen default value 00 0 0 0 0 1 1 a[7:0] creg8[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 08 adcmutel reserved adcgainl[4:0] default value 0 0 010010
AV2722 (preliminary) 21-29 january 22, 2004 address 09, adc path right channel gain a nd mute control register (creg9[7:0]) adcmuter: adc right ch annel mute control. 0: do not mute the adc right-channel (default). 1: mute the adc right channel, sdo will shif t out all zero data in the right channel. adcgainr[4:0]: 5-bit adc rightchannel input gain (volume) control. the default value of adcgainr[4:0] is binary 10010 which is corresponding to 0 db. address 0a, adc power down cont rol register (creg10[7:0]) adclpwdn: adc left channel power down. 0: do not shut down power of adc left channel. 1: shut down power of adc left channel (default) adcrpwdn: adc right channel power down 0: do not shut down power of adc right channel. 1: shut down power of a dc right channel (default). pwdnmicbias: microphone bias circuit power down. 0: do not shut down microphone bias circuit (default). 1: shut down power of microphone bias circuit. address 0b, adc left and righ t microphone gain control register (creg11[7:0]) useadcl: use adc micr ophone left channel. 0: adc left channel microphone is not used (default). 1: adc left channel microphone is used. a[7:0] creg9[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 09 adcmuter reserved adcgainr[4:0] default value 0 0 0 10010 a[7:0] creg10[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 0a reserved adclpwdn adcrpwdn pwdnmicbias default value 00000 1 10 a[7:0] creg11[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex 0b reserved useadcl micgainl[1:0] reserved useadcr micgainr[1:0] default value 0 000 0 0 00
AV2722 (preliminary) 22-29 january 22, 2004 by default, adc microphone left channel is shut down (adcl pwdn=1). if adclpwdn is programmed to ?0?, this bit must be programmed to ?1? to use the left channel microphone micgainl[1:0]:2-bit left channel microphone gain 00: no gain increase (default). 01: 6 db gain increase for the left channel microphone input. 10: 12 db gain increase for the left channel microphone input. 11: 18 db gain increase for the left channel microphone input. useadcr: use adc micr ophone right channel. 0: adc left channel microphone is not used (default). 1: adc right channel microphone is used. by default, adc microphone right channel is shut down (adcrp wdn=1). if adcrpwdn is programmed to ?0?, this bit must be programmed to ?1? to use the right channel microphone. micgainl[1:0]:2-bit right channel microphone gain. 00: no gain increase (default). 01: 6 db gain increase for the right channel microphone input. 10: 12 db gain increase for the right channel microphone input. 11: 18 db gain increase for the right channel microphone input. address 0c, software reset cont rol register (creg12[7:0]) sofrst: [1:0]: software reset. 0: no software reset. 1: software reset. digital interpolation filter characteristics (to be inserted) digital filter frequency response (to be inserted) a[7:0] creg12[7:0] bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex0c reserved sofrst default value 0000000 0
AV2722 (preliminary) 23-29 january 22, 2004 1 2 3 4 5 6 7 22 23 24 25 26 27 28 vdd sc sdi sdo sfda sfad hpvr vss xck rs/ sda scl csb mode AV2722 8 9 10 11 12 13 14 vddh houtl houtr aoutl vssh aoutr vdda 15 16 17 18 19 20 21 hpdet ainl ainr vcm micbias vssa vssa 220uf 10uf 10uf 220uf 10uf 0.1uf 47k 47k 10uf 0.1uf 20k 100k 22uf 20k 20k 1000pf 220pf 10uf 5.6k 5.6k 220pf 1uf unpop unpop 5.6k 5.6k 220pf 1uf unpop unpop left channel lpf right channel lpf left or right channel lpf 680 ohm 47uf 0.1uf 3-wire interface, mode is not connected. 2-wire interface, mode is connected 47k 47k 3.3 v or gnd audio serial i/o interface 3.3v 47uf 0.1uf 3.3v for microphone input, remove 220pf capacitor and 5.6k resistors, short r1 r1 to microphone to headphone ground in capless mode, otherwise, no connect connection example
AV2722 (preliminary) 24-29 january 22, 2004 absolute maximum ratings notes: absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. symbol characteristics min max units v dd vdda vddh power supply voltage (measured to vss) -0.3 +3.6 v v id digital input applied voltage 1 gnd-0.3 v dd +0.3 v v ia analog input applied voltage 1 gnd-0.3 v dda +0.3 v v o digital output voltage gnd-0.3 v dd +0.3 v t a operating temperature range -25 +85 o c tstg storage temperature before soldering 30 o c t stor storage temperature after soldering -65 +150 o c t j junction temperature (plastic package) -65 +150 o c tsol lead soldering temperature (10 sec., 1/4? from pin) 240 o c tvsol vapor phase soldering (1 minute) 180 o c
AV2722 (preliminary) 25-29 january 22, 2004 recommended operating conditions electrical chracteristics symbol characteristics min typical max units v dd v dda v ddh power supply voltage 3.6 v vss v ssa v ssh ground 0v t a ambient operating temperature range 0 70 o c parameter characteristics / test conditions min typ max units digital input v ih digital input voltage, logic high, ttl compatible inputs. 2.0 v dd v v il digital input voltage, logic low, ttl compatible inputs v ss 0.8 v i ih digital input current, logic high, (v in =4.0v) tbd a i il digital input current, logic low, (v in =0.4v) tbd a serial audio port timing (slave mode) tsc sc pulse cycle time 100 ns tsc h sc pulse width, high 50 ns tsc l sc pulse width, low 50 ns t su audio data setup time with respect to rising edge of sc 30 ns t hd audio data hold time with respect to rising edge of sc 30 ns tsfsc audio sfsetup time with respect to rising edge of sc 30 ns tscsf audio sf hold time wi th respect to rising edge of sc 30 ns serial audio port timing (master mode) tm su sdi audio data setup time 10 ns tm hd sdi audio data hold time 10 ns
AV2722 (preliminary) 26-29 january 22, 2004 tmsfd sfda/sfad propagation de lay from sc falling edge 10 ns tmsdod sdo propagation delay from sc falling edge 10 ns serial command port ti ming (mpu type mode) t scl scl cycle time 100 ns t sclh scl high time 80 ns t scll scl low time 40 ns t sdasu sda to scl setup time 20 ns t sdahd scl to sda hold time 20 ns t csbl csb pulse low time 20 ns t csbh csb pulse high time 20 ns tsclcsb scl rising edge to csb rising edge 20 ns tcsbscl csb rising edge to scl rising edge 20 ns serial command port timing (i2s mode) fsc scl clock frequency 100 khz tsu;sta start condition setup time 4.7 s thd;sta start condition hold time 4.0 s tsu;sto stop condition setup time 4.0 s tlow scl low time 4.7 s thigh scl high time 4.0 s tr scl and sda rise time 1.0 s tf scl and sda fall time 0.3 s tsu;dat data setup time 250 ns thd;dat data hold time 0 ns tvd;dat scl low to data output valid 3.4 s tbuf bus free time 4.7 s adc line input vin(line) input signal level for line input (0db) tbd vrms snr a-weighted, 0 db gain @fs=48khz tbd db a-weighted, 0 db gain @fs=96khz tbd db a-weighted, 0 db gain @fs=48khz, vdda=2.7v tbd db parameter characteristics / test conditions min typ max units
AV2722 (preliminary) 27-29 january 22, 2004 thd total harmonic distortion tbd db dr dynamic range, a weighted -60 db full scale input tbd db psrr power supply rejection ra tio, 1khz 100 mvpp tbd db power supply rejection ratio, 20 hz to 20khz 100 mvpp tbd db adc channel separation (@ 1khz input) tbd db mute attenuation (0 db @ 1khz input) tbd db r inline input resistance, 0 db gain tbd input resistance, 12 db gain tbd c inline input capacitance tbd pf adc microphone input @ 0db gain, fs=48khz vin(mic) input signal level for microphone input (0db) tbd vrms snr a weighted, 0 db gain tbd db thd 0db input, 0 db gain tbd db psrr power supply rejection ra tio, 1khz 100 mvpp tbd db power supply rejection ratio, 20 hz to 20khz 100 mvpp tbd db dr dynamic range, a weighted, -60 db full scale input tbd db mute attenuation (@0db, 1khz input) tbd db r inmic input resistance tbd c inmic input capacitance tbd pf microphone bias v micbias microphone bias voltage tbd v i micbias microphone bias current tbd pf vn output noise voltage (1k to 20 khz) tbd nv/hz 1/2 line output for dac playback (load =10k , 50pf) vout 0 db full scale output voltage tbd vrms snr a-weighted, 0 db gain @fs=48khz tbd db a-weighted, 0 db gain @fs=96khz tbd db a-weighted, 0 db gain @fs=48khz, vdda=2.7v tbd db dr dynamic range, -60 db full scale input tbd db parameter characteristics / test conditions min typ max units ? ? ? ?
AV2722 (preliminary) 28-29 january 22, 2004 test conditions : vdd, vddh, vdda= 3.3 v, vss=0 v, t a 25 o c, slave mode, 48 khz sampling rate, 256 fs. thd total harmonic distortion, 1khz, 0dbfs tbd db total harmonic distortion, 1khz, -3dbfs tbd db psrr power supply rejection ra tio, 1khz 100 mvpp tbd db power supply rejection ratio, 20 hz to 20khz 100 mvpp tbd db mute attenuation (1khz, 0 db) tbd db stereo headphone output vout 0 db full scale output voltage tbd vrms pout output power with r l = 32 , tbd mw output power with r l = 16 , tbd mw snr signal to noise ratio, a-weighted tbd db thd 1khz, with r l = 32 , pout =10mw rms (-5db) tbd % db 1khz, with r l = 32 pout = 20 mw rms (-2db) tbd % db psrr power supply rejection ra tio, 1khz 100 mvpp tbd db power supply rejection ratio, 20 hz to 20khz 100 mvpp tbd db mute attenuation 1khz, 0 db tbd db parameter characteristics / test conditions min typ max units ? ? ? ?
AV2722 (preliminary) 29-29 january 22, 2004 b e e1 e d l a 28 pin ssop (10.2 x 5.3 x 1.75 mm) -c- 0.10 l1 c 0.25 seating plane a2 a1 gauge plane 1 14 15 28 packaging information symbols dimensions (mm) min nom max a ----- ----- 2.0 a1 0.05 0.13 0.25 a2 1.65 1.75 1.85 b 0.22 ----- 0.38 c 0.09 ----- 0.25 d 9.90 10.20 10.50 e 7.40 7.80 8.20 e 0.65 bsc e1 5.00 5.30 5.60 l 0.55 0.75 0.95 l1 1.25 ref 0 o 4 o 8 o ref: jedec.95, mo-150

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